1. Field of the Invention
This invention relates to a scheme to resolve and convert Multi-Level Cell (MLC) Non-Volatile Memory (NVM) into multi-bits per NVM cell. In particular, the MLC threshold voltages are divided into several threshold voltage groups containing multiple threshold voltage sub-groups. The multiple threshold voltage subgroups in each group are sensed and resolved by applying one correspondent gate voltage to each one of the main groups. By applying multiple correspondent gate voltages to the entire main groups of MLC NVM cells, the multi-bit information in NVM cells can be accurately and efficiently obtained.
2. Description of the Related Art
Semiconductor Non-Volatile Memory (NVM), and particularly Electrically Erasable, Programmable Read-Only Memories (EEPROM), exhibit wide spread applicability in a range of electronic equipments from computers, to telecommunications hardware, to consumer appliances. In general, EEPROM serves a niche in the NVM space as a mechanism for storing firmware and data that can be kept even with power off and can be altered as needed. The flash EEPROM may be regarded as a specifically configured EEPROM that may be erased only on a global or sector-by-sector basis.
Data is stored in an EEPROM cell by modulating its threshold voltage, Vth, of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) through the injection of charge carriers into the charge-storage layer from the channel of the MOSFET. For example, with respect to an N-channel MOSFET, an accumulation of electrons in the floating gate, or in a dielectric layer above the FET channel region, causes the MOSFET to exhibit a relatively high threshold voltage Vth. In Single Level Cell (SLC) semiconductor NVM operations, the cells with higher threshold voltages are “off” and the cells with lower threshold voltages are “on”, when applying a gate voltage between two groups of “high” and “low” threshold voltage levels to the gates of the NVM cells.
In MLC semiconductor NVM operation, multi-bit information stored in NVM cell is represented by the states of multiple NVM cell threshold voltage levels. The number of bits stored in an EEPROM cell is given by the number of resolvable threshold voltage levels, i.e., Number of Bits=log2 (numbers of resolvable threshold voltage levels). The threshold voltage levels of MLC cells are sensed by applying a single gate voltage or multiple gate voltages to the gates of NVM cells with voltage biases on the source and drain electrodes of NVM cells, respectively.
One conventional way of reading out bit information in MLC NVM cells is the single gate voltage scheme, where a constant gate voltage is applied to the gates of MLC NVM cells with biased source and drain. Since the response currents of NVM cells are the function of voltage difference between the applied gate voltage and threshold voltage of NVM cell, Vg−Vth, the states of MLC NVM cells can be determined by directly comparing the cell responding current with several preset reference currents. For the example of a two-bit MLC NVM cells in NOR-type flash, the threshold voltages of NVM cells are divided into four groups for representing (11), (10), (01), and (00) as shown in FIG. 1. A constant gate voltage Va, between the groups of threshold voltages of (01) and (00) is applied to the gates of MLC NVM cells. The NVM cell response currents are ID(11)>ID(10)>ID(01)>ID(00) for the voltage differences of Va−Vth(11)>Va−Vth(10)>Va−Vth(01)>Va−Vth(00), where ID(11), ID(10), ID(01), ID(00), and Vth(11), Vth(10), Vth(01), Vth(00) are the response currents and the threshold voltages for the four groups, respectively. Note that the currents for the groups of (11), (10), and (01) are the “on” currents while the current for group of (00) is the “near-on or off” current for the threshold voltage near the applied voltage Va as shown in FIG. 1. Three reference currents are chosen in between the cell response currents of the four groups of NVM cells applied with the gate voltage Va. By comparing the cell response currents with the three reference currents under the condition of applying gate voltage Va to the gates of NVM cells, the threshold voltages of MLC NVM cells can be determined to be in the specific belonging group and consequently converted to the stored bit information by their representing state of the NVM cells.
Although this scheme is the fastest way to determine the stored bits in the MLC NVM cells by applying only one single gate voltage, the numbers of resolvable threshold voltage levels are limited by the sensing current accuracy. Furthermore, the characteristics of the responding NVM device electric current to an applied gate voltage show electric current degeneracy in the two ends of operation regions where a small insignificant leakage current is generated for an applied gate voltage below the cell threshold voltage and the NVM cell “on” currents are saturated beyond a certain applied gate voltage in the strong inversion region. The current degeneracy further limits the sensible current range to resolve the threshold voltages of NVM cells below and beyond the applied gate voltage. Usually, the resolvable threshold voltage range with a single applied gate voltage is around few volts for a typical NOR-type flash.
Another conventional way of reading out bit information in MLC NVM cells is the varying step gate voltage scheme where multiple gate voltages are applied to the gates of MLC NVM cells. When an applied gate voltage is greater than the threshold voltages of the NVM cells, the NVM cells are turned “on”, and while an applied gate voltage is less than the threshold voltages of the NVM cells the NVM cells are “off”. The “on” and “off” states are sensed by a “on” current regardless the amounts of the “on” currents from the voltage differences of the applied gate voltage and the cell threshold voltages. Thus in this scheme, information coming out from the output of the sense amplifier for an NVM cell indicates that the threshold voltages of NVM cells are greater (or less) than the applied gate voltage. For an example of a conventional 2-bit per cell MLC NAND-type flash as shown in FIG. 2, three gate voltages in between the four groups of NVM threshold voltages representing (11), (10), (00), and (01) are applied to the gates of NVM cells. After completion of the three step gate voltage sequence, the two bit information stored in NVM cells are converted from the outputs of the sense amplifiers by a pre-designed logic circuitry.
In the previous U.S. Pat. Nos. 7,400,527 and 7,606,069, a Digital-to-Analog Converter (DAC) is applied to generate multiple correspondent gate voltages to the NVM cells. When the NVM cells are turned “on” from an “off” state in response to an applied incremental step gate voltage from the previous applied gate voltage the correspondent bits in the DAC for representing the state are written into the read data buffer. Although the multiple-gate-voltage scheme can resolve much smaller threshold voltage level compared with the single gate voltage scheme, the applications of multiple voltages to the gates of NVM cells require a longer time for an increasing number of applied gate voltages. In one 4-bit per cell MLC NVM design, the total 15-step gate voltage sequence to read out the storing bits in the MLC NVM cells requires more than several microseconds (>10−6 s) in contrast to about a hundred nanoseconds (˜10−7 s) of a typical 2-bit per cell NOR-type MLC flash.
In order to resolve the sensing limitation posed in the single gate voltage scheme and the slow bit reading out speed in the multiple-gate-voltage scheme as mentioned above, we disclose a new bit reading out scheme in MLC NVM for achieving a higher threshold voltage resolution and a higher reading-out speed.